1. Field of the Invention
The present invention relates to a display system suitable for use with a digital computer, and more particularly to a display system with a data structure which is suited to be microprogram-controlled.
2. Description of the Prior Art
A display system suitable for use with an electronic computer generally comprises a data control unit for controlling the exchange of data with an external information source such as an electronic computer or a keyboard, a refresh memory for storing a field of display data with the aid of the data control unit and reading out the data in synchronism with a display timing, a video control unit for converting the display data read out of the refresh memory to a display video signal, a viewer which receives the video signal from an output of the video control unit and displays it on a screen of a cathode ray tube (CRT) as a visible image, and a timing control unit for producing a control timing signal for the data control unit, an I/O timing signal for the refresh memory, a signal output timing signal for the video control unit and a display timing signal for the viewer.
In this type of the display system, as the field of application thereof was broadened, the content of processing has become versatile and the display function has also become versatile. Thus, in order to meet the processing and display functions by a pure hardware configuration, there necessarily results a large scale configuration. As an approach thereto, it has been proposed to incorporate a microcomputer in the data control unit of the display system to increase the flexibility of the content of processing by the microprogram control by the microcomputer or reduce the amount of hardware.
An example of the display system incorporating the microcomputer is shown in Japanese Patent Appln. Kokai (Laid-Open) No. 82134/77 which was filed Dec. 29, 1975, assigned to the assignee of the present invention and was laid open July 9, 1977. It corresponds to U.S. Application Ser. No. 754,997 now Pat. No. 4,104,624 filed Dec. 28, 1976. The display system disclosed in the U.S. application Ser. No. 754,997 now U.S. Pat. No. 4,104,624 comprises a data control unit, a refresh memory unit and a timing control unit which are interconnected via a common address bus and a common data bus, and the data control unit includes a microprocessor and a microprogram memory. While the refresh memory unit stores display data from an external information source, the data transfer to and from the external information source is carried out under the microprogram control by the microprocessor and the microprogram memory in the data control unit. The microprocessor is, in general, a byte machine which handles the information by one byte or eight bits. On the other hand, the display data is generally at least 16-bit information or 2-byte information as the number of display information increases and the number of display modes of the display information (e.g. designation of color, size or brightness and presence or absence of blinking) increases. Since the data control unit and the refresh memory are interconnected via the common address bus and data bus, the refresh memory can only receive the data one byte at a time. On the other hand, the display data is of one-word (two-byte) configuration as described above and hence it is desirable to read the display information from the refresh memory by two bytes (equal to 16 bits) at a time in order to simplify the construction. (The readout timing is in synchronism with the display timing.) Accordingly, in the U.S. application Ser. No. 754,997 now U.S. Pat. No. 4,104,624, the refresh memory unit is divided into an upper byte memory and a lower byte memory, and for each access by the data control unit (data read or data write), the upper or lower byte memory is specified for each byte and one-byte information of the two-byte data is written into a specified address of that memory. Thereafter, the other one-byte information is written into a specified address of the other memory. Similarly, when data is to be read from the refresh memory unit into the data control unit, the content at a specified address of the upper or lower byte memory is read one byte at a time. When it is necessary to read out two-byte display information, both the upper and lower byte memories are addressed simultaneously and the two-byte display data is temporarily stored in a display register, which is then read out by the video control unit. In this manner, in the display system disclosed in the U.S. application Ser. No. 754,997 now U.S. Pat. No. 4,104,624, the data of the refresh memory unit is read or written by one byte at a time for the access by the data control unit while it is read by two bytes (one word) at a time for the readout for display. Therefore, the overall construction of the display system is simplified. Furthermore, since any desired processing can be performed by modifying the microprogram, the system can be used for general purposes.
However, since the I/O processing (access) from the data control unit can only be carried out one byte at a time as described above, a problem occurs in that much time is required to edit the content displayed in the viewer. When image editing is to be carried out, it is necessary to rewrite the one-byte information stored in the lower byte memory and the other one-byte information stored in the upper byte memory, for each display data. Thus, the data control unit must alternately access, by one byte at a time, all of the necessary display data (multiple of one word). As is described in detail in the U.S. application Ser. No. 754,997, now U.S. Pat. No. 4,104,624 when the readout operation for display and the I/O operation due to the access by the data control unit are alternately carried out in a time division manner, it is necessary to store an information indicative of the current address at which the I/O operation is carried out in preparation for the next I/O operation when the operation moves from the I/O operation to the read operation for display. For this reason, the prior art display system involves a problem that a procedure for editing the information displayed on the screen is complex and high speed editing cannot be attained.